Howard A. Landman

520 N. Sherwood #24, Ft. Collins, CO 80521
Cell: (970) 980-1660
Email: howard@riverrock.org
Skype: howard_landman


Education


Experience
3/08 to present: Independent Consultant
Client List:

1/05 to 3/08: Manager, Physical Design
Ageia Technologies, Santa Clara, CA (acquired by Nvidia 2/08)
Led the physical design of Ageia's 90nm 2nd-generation PhysX chip, including team of 7 engineers in Bangalore India. Selected tools, developed design methodology and coding guidelines, and took chip to completion. Introduced voltage island and other power reduction methods and improved DFM/DFY approach.

3/02 to 1/05: Independent Consultant
Client List:

3/99 to 2/02: Senior Design Engineer
Vitesse Semiconductor, ANP division (formerly SiTera Inc.), Longmont, CO
Formal verification, technology evaluation, electromigration analysis, clock distribution, DRC/ERC runset development, and some RTL coding for the IQ2000 & IQ2200 network processors. Worked on 14 total tapeouts. Tools used include Perl, Tcl, Apollo/Milkyway, Hercules, Design Verifyer (Chrysalis), Design Compiler, Tetramax, VCS, Calibre, Verplex LEC.

11/96 to 1/99: Manager, Synthesis & Physical Design, Processor Development
Toshiba America Electronic Components, San Jose, CA
Led the logic synthesis and physical design of the processor for the Sony Playstation 2 "Emotion Engine" (first commercial 128-bit microprocessor). 7 people in my team. Developed and managed back-end schedule with only 14% slip. Much travel to Japan and coordination with Japanese managers & engineers. Wrote Logic Design Rules spec and co-wrote RTL Design Guidelines. Spearheaded use of Ambit (synthesis) and Chrysalis (formal verification) tools. First silicon was 100% functional; second silicon (speedup) shipped in development systems; third silicon (shrink & cost reduction) shipped over 23 million units.

11/92 to 11/96: Senior CAD Engineer
HaL Computer Systems, Campbell, CA (later acquired by Fujitsu)
Corporate logic synthesis guru. Also developed Verilog library & validation procedure; methodologies and tools for post-layout backannotation, electromigration analysis, antenna-rule checking, netlist partitioning, & FSM coverage analysis. Responsible for QA of cell libraries. Heavy use of Perl.

5/91 to 11/92: Senior CAD Engineer
Crosspoint Solutions, Santa Clara, CA
Responsible for logic-synthesis-related products and libraries. Developed AI system in Perl and Prolog to generate optimal cell layouts from transistor netlists, which successfully replaced a human designer.

4/88 to 5/91: Senior CAD Engineer
Sun Microsystems, Mountain View, CA
Lead EDA engineer for MicroSparc (Tsunami) microprocessor: planned and helped implement entire tools flow. Patented method for handling multi-cycle paths consistently in timing analysis, simulation, and synthesis. Evaluated and benchmarked commercial logic synthesis tools. Was Sun's corporate "Synopsys guru".

1/86 to 4/88: Senior CAD Software Engineer
Intel Corp., ASIC Systems, Chandler, AZ
Evaluated silicon compilers in relation to Intel's processes, methods, and ASIC strategy. Led joint project with SCS. Developed netlist translators using lex, yacc, and C. Introduced UNIX into ASIC group, administered VAX/Ultrix system. Headed Software Quality Task Force.

9/84 to 11/85: Software Engineer
Silicon Compilers Inc., San Jose, CA
Wrote CMOS PLA, PAL, and ROM compilers and PLA optimizer for SCI's Genesil silicon compiler. Incorporated Espresso into Genesil. Maintained NMOS PLA, PAL, and ROM compilers. All code in C and extensions of C.

6/82 to 8/84: VLSI/CAD Designer
Metheus Corporation, Hillsboro, OR
Principal SW engineer for 10 programs in Metheus' CAE workstation. All work in C, UNIX. Negotiated with foundries leading to technology exchange agreements. Some technical marketing work with much travel.


Engineering Publications

"Rebuttal of overtaking VEST", Mar. 2007
http://eprint.iacr.org/2007/124

"Implementing BIST and Repair in a Memory Intensive Design", MUSIC India, Nov. 2006

"VEST Hardware-Dedicated Stream Ciphers", June 2005
http://www.ecrypt.eu.org/stream/ciphers/vest/vest.pdf

"Stability Analysis of a Complete RTL-to-GDS2 Design Flow", Magma Fusion Users Group, Sept. 2003

"A High Bandwidth Superscalar Microprocessor for Multimedia Applications", ISSCC 1999

"Visualizing the Behavior of Logic Synthesis Algorithms", 1998 Synopsys User's Group.

"Paths to Nanotechnology", chapter 6 in Krummenacker & Lewis (eds.), Prospects in Nanotechnology: Toward Molecular Manufacturing, Wiley 1995

U.S. Patent 5,191,541: Method and Apparatus to Improve Static Path Analysis of Digital Circuits, March 2, 1993

"Low-level Logic Synthesis", IDEA '91 Conference

"Design Environments at Sun: Logic Synthesis", Sun User's Group 89

"Logic Synthesis at Sun", CompCon Spring 89

"OPUSI: An Optical Digital Position Sensor", ICCAD 83 Digest of Technical Papers, September 1983

"Integrating Foundry Processes into the Engineering Workstation", Electro/83 Professional Program, April 1983

Automatic Layout of Optimized PLA Structures, Masters Thesis, U.C. Berkeley, 1982.

"PLA Tools" in Berkeley VLSI Tools, Bob Mayo (ed.), Computer Science Division, U.C. Berkeley 1982

"A RISCy Approach to VLSI", VLSI Design, 4th quarter 1981.

"VLSI Implementations of a Reduced Instruction Set Computer", CMU Conference on VLSI Systems and Computations, 1981


Industry Activities:

Program Committee, IEEE Symposium on Computational Intelligence and Games, 2005-2006

Board of Technical Advisors, PicoCraft Design Systems, 2004-2007

Board of Editorial Advisors, Integrated System Design magazine, 1997-99

Technical Program Committee, Synopsys Users Group, 1994-96

Senior Associate, Foresight Institute

Reviewer for Theoretical Computer Science and Journal of Combinatorial Theory A

Senior Member IEEE; Member MAA, NCSE


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