I am seeking a management position leading either an integrated circuit
design or the CAD/EDA tools and methodologies supporting one.
- 4/02 to 8/02: consultant for
Calix Networks,
Petaluma, CA
- Evaluated Magma Blast RTL synthesis tool and
developed module layout flows using Magma Blast Fusion.
Responsible for area feasibility studies, clock skew,
timing closure, etc.
- 3/99 to 2/02: Senior Design Engineer
Vitesse Semiconductor,
ANP division (formerly SiTera Inc.),
Longmont, CO
- Staff position responsible for
formal verification, technology evaluation, electromigration
analysis, clock distribution, DRC/ERC runset development, and
some RTL coding for the
IQ2000 &
IQ2200
network processors.
Tools used include Perl,
Apollo/Milkyway, Hercules, Design Verifyer (Chrysalis),
Design Compiler, Tetramax, VCS,
Calibre.
- 11/96 to 1/99:
Manager, Synthesis & Physical Design, Processor Development
Toshiba America Electronic Components,
San Jose, CA
- Managed the logic synthesis and physical design of
the R5900 processor,
the first commercial 128-bit microprocessor and
the heart of the Sony
Playstation 2
"Emotion Engine".
First silicon was 100% functional;
second silicon (speedup) shipped in development systems;
third silicon (shrink & cost reduction) went into Japanese, American and
European PS2s and has shipped over 23 million units.
7 people in my team.
Developed and managed back-end schedule with only 14% slip.
Much travel to Japan and coordination with Japanese managers & engineers.
Wrote Logic Design Rules spec and co-wrote RTL Design Guidelines.
Spearheaded use of Ambit (synthesis) and Chrysalis
(formal verification) tools.
- 11/92 to 11/96:
Senior CAD Engineer
HaL Computer Systems, Campbell, CA (later acquired by
Fujitsu)
- Corporate logic synthesis guru.
Also developed Verilog library & validation procedure;
methodologies and tools for post-layout backannotation,
electromigration analysis, antenna-rule checking,
netlist partitioning, & FSM coverage analysis.
Responsible for QA of cell libraries.
Heavy use of Perl.
- 5/91 to 11/92:
Senior CAD Engineer
Crosspoint Solutions, Santa Clara, CA
- Responsible for logic-synthesis-related products and libraries.
Developed AI system in Perl and Prolog to generate optimal cell layouts
from transistor netlists,
which successfully replaced a human designer.
- 4/88 to 5/91:
Senior CAD Engineer
Sun Microsystems, Mountain View, CA
-
Lead EDA engineer for MicroSparc (Tsunami) microprocessor:
planned and helped implement entire tools flow.
Patented method for handling multi-cycle paths consistently
in timing analysis, simulation, and synthesis.
Evaluated and benchmarked commercial logic synthesis tools.
Was Sun's corporate "Synopsys guru".
- 1/86 to 4/88:
Senior CAD Software Engineer
Intel Corp., ASIC Systems, Chandler, AZ
- Evaluated silicon compilers in relation
to Intel's processes, methods, and ASIC strategy.
Led joint project with SCS.
Developed netlist translators using lex, yacc, and C.
Introduced UNIX into ASIC group, administered VAX/Ultrix system.
Headed Software Quality Task Force.
- 9/84 to 11/85:
Software Engineer
Silicon Compilers Inc., San Jose, CA
- Wrote CMOS PLA, PAL, and ROM compilers and PLA optimizer
for SCI's Genesil silicon compiler.
Incorporated Espresso into Genesil.
Maintained NMOS PLA, PAL, and ROM compilers.
All code in C and extensions of C.
- 6/82 to 8/84:
VLSI/CAD Designer
Metheus Corporation, Hillsboro, OR
- Principal SW engineer for 10 programs in Metheus' CAE workstation.
All work in C, UNIX.
Negotiated with foundries leading to technology exchange agreements.
Some technical marketing work with much travel.
- 6/81 to 6/82:
Director of Software Engineering
SynMos Corporation, Palo Alto, CA
- Developed and maintained CAD environment for IC design,
including configuration of mainframe and workstations
and integration of software packages.
Helped teach introductory VLSI design courses;
designed standard library cells for use in class projects.
Designed test patterns and circuits to evaluate fabrication quality, and helped
screen incoming wafers.
- 1979 to 1981 (summer & part-time):
Research Intern
Xerox Corporation,
Palo Alto Research Center, Palo Alto, CA
- Enhanced interactive text/graphics system
for managing run data for NMOS fab facility.
Designed circuits and test patterns for characterization.
Publications, Presentations, and Quotes
"VEST Hardware-Dedicated Stream Ciphers",
submitted to the Ecrypt Stream Cipher Project.
"A Simple FSM-Based Proof of the Additive Periodicity
of the Sprague-Grundy Function of Wythoff's Game",
More Games of No Chance.
This was based on my talk at
MSRI
in 2000;
streaming video of the talk is available from www.msri.org.
"A High Bandwidth Superscalar Microprocessor for Multimedia Applications",
ISSCC 1999
"Visualizing the Behavior of Logic Synthesis Algorithms",
1998 Synopsys User's Group. Available online in
Postscript or
FrameMaker MIF formats.
Quoted in article about logic synthesis and floorplanning,
Design Wave magazine, May 1998, p.75 (in Japanese)
Quoted in "Readers Speak Out on DSM: Part 2,
in Integrated Systems Design magazine, December 1997
Quoted in "Verilog
Won and VHDL Lost? You Be The Judge", John Cooley's article about the design contest
at Synopsys User's Group 1995,
in Integrated Systems Design magazine, July 1995, pp.56-60.
I took 3rd place.
"Eyespace Values in Go", in Richard J. Nowakowski (ed.),
Games of No Chance : Combinatorial Games at MSRI, 1994
(Mathematical Sciences Research Institute Publications, No 29)
"Paths to Nanotechnology", chapter 6 in Krummenacker & Lewis (eds.),
Prospects in Nanotechnology: Toward Molecular Manufacturing,
Wiley 1995
(Based on my talk at the First General Conference on Nanotechnology in 1992).
U.S. Patent 5,191,541: Method and Apparatus to Improve Static Path Analysis of
Digital Circuits, March 2, 1993
Quoted in "Designers must look beyond the obvious to discover the
promise of synthesis", Computer Design, June 1991, p.90-91
"Low-level Logic Synthesis", IDEA '91 Conference
"Design Environments at Sun: Logic Synthesis", Sun User's Group 89
"Logic Synthesis at Sun", CompCon Spring 89
"OPUSI: An Optical Digital Position Sensor",
ICCAD 83 Digest of Technical Papers, September 1983
"Integrating Foundry Processes into the Engineering Workstation",
Electro/83 Professional Program, April 1983
Automatic Layout of Optimized PLA Structures,
Masters Thesis, U.C. Berkeley, 1982.
Republished as "PLA Tools" in Berkeley VLSI Tools, Bob Mayo (ed.),
Computer Science Division, U.C. Berkeley 1982
"A RISCy Approach to VLSI", VLSI Design, 4th quarter 1981.
More polished version of "VLSI Implementations of a Reduced Instruction Set Computer",
CMU Conference on VLSI Systems and Computations, 1981
Industry Activities:
ITCOM program committee, 2001
Board of Editorial Advisors,
Integrated System Design magazine,
1997-99
Synopsys Users Group Technical Program Committee, 1994-96
Senior Associate,
Foresight Institute
Occasional reviewer for Theoretical Computer Science
and Journal Of Combinatorial Theory A
Hobbies and Interests:
Aikido (black belt), Tai Chi, Yoga;
guitar, songwriting, poetry, MIDI;
Japanese, German; Go;
climbing, caving, hiking;
scuba, kayaking;
mathematics; nanotechnology; quantum computing;
photography, data visualization
©2005 Howard A. Landman, all rights reserved